317 lines
13 KiB
C
317 lines
13 KiB
C
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/******************************************************************************
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*(C) Copyright 2018 EIGENCOMM International Ltd.
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* All Rights Reserved
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******************************************************************************
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* Filename: i2s.h
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*
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* Description:
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*
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* History: Rev1.0 2020-02-24
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*
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* Notes: i2s driver
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*
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******************************************************************************/
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#ifndef BSP_I2S_H
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#define BSP_I2S_H
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/*----------------------------------------------------------------------------*
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* INCLUDES *
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*----------------------------------------------------------------------------*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "stdio.h"
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#include "stdlib.h"
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#include "string.h"
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#include "ec7xx.h"
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#include "bsp.h"
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/*----------------------------------------------------------------------------*
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* MACROS *
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*----------------------------------------------------------------------------*/
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// Sample rate that 618 supports
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#define SAMPLE_RATE_8K 0x0
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#define SAMPLE_RATE_16K 0x1
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#define SAMPLE_RATE_22_05K 0x2
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#define SAMPLE_RATE_24K 0x3
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#define SAMPLE_RATE_32K 0x4
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#define SAMPLE_RATE_44_1K 0x5
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#define SAMPLE_RATE_48K 0x6
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#define SAMPLE_RATE_96K 0x7
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// I2S DMA chain num
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#define I2S_DMA_TX_DESCRIPTOR_CHAIN_NUM 20
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#define I2S_DMA_RX_DESCRIPTOR_CHAIN_NUM 20
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// I2s Event
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#define ARM_I2S_EVENT_TRANSFER_COMPLETE (1UL << 0)
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#define ARM_I2S_EVENT_DATA_LOST (1UL << 1)
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#define ARM_I2S_EVENT_MODE_FAULT (1UL << 2)
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// DMA I2S Request ID
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#define RTE_I2S0_DMA_TX_REQID DMA_REQUEST_USP0_TX
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#define RTE_I2S0_DMA_RX_REQID DMA_REQUEST_USP0_RX
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#define RTE_I2S1_DMA_TX_REQID DMA_REQUEST_USP1_TX
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#define RTE_I2S1_DMA_RX_REQID DMA_REQUEST_USP1_RX
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#define RTE_I2S2_DMA_TX_REQID DMA_REQUEST_USP2_TX
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#define RTE_I2S2_DMA_RX_REQID DMA_REQUEST_USP2_RX
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// I2S control bits
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#define I2S_CTRL_TRANSABORT (1UL << 0) // I2S trans abort
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#define I2S_CTRL_SAMPLE_RATE_SLAVE (1UL << 1) // I2S sample rate setting, used in ec618 slave mode
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#define I2S_CTRL_SAMPLE_RATE_MASTER (1UL << 2) // I2S sample rate setting, used in ec618 master mode
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#define I2S_CTRL_SET_TOTAL_NUM (1UL << 3) // Audio source total num
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#define I2S_CTRL_DATA_FORMAT (1UL << 4) // I2S data format
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#define I2S_CTRL_SLOT_CTRL (1UL << 5) // I2S slot ctrl
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#define I2S_CTRL_BCLK_FS_CTRL (1UL << 6) // I2S bclk fs ctrl
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#define I2S_CTRL_DMA_CTRL (1UL << 7) // I2S dma ctrl
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#define I2S_CTRL_INT_CTRL (1UL << 8) // I2S int ctrl
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#define I2S_CTRL_TX_DESCRIPTOR (1UL << 9) // I2S tx dma descriptor num set
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#define I2S_CTRL_RX_DESCRIPTOR (1UL << 10) // I2S rx dma descriptor num set
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#define I2S_CTRL_I2SCTL (1UL << 11) // I2S control
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#define I2S_CTRL_AUTO_CG_CTRL (1UL << 12) // I2S auto cg ctrl
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#define I2S_CTRL_INIT (1UL << 13) // I2S init
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#define I2S_CTRL_START_STOP (1UL << 14) // I2S audio play start/stop ctrl
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#define I2S_CTRL_DMA_TRUNK_NUM (1UL << 15) // I2S dma trunk num for every transfer
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/*----------------------------------------------------------------------------*
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* DATA TYPE DEFINITION *
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*----------------------------------------------------------------------------*/
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typedef void (*i2sCbEvent_fn) (uint32_t event, uint32_t arg); // i2s callback event.
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#if (VOLTE_EC_OWN_BOARD_SUPPORT)
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typedef void (*i2sSlp1Cb_fn)();
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#endif
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// I2S IRQ
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typedef struct
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{
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IRQn_Type irqNum; // I2S IRQ Number
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IRQ_Callback_t cbIrq;
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} I2sIrq_t;
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// I2S DMA
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typedef struct
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{
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DmaInstance_e txInstance; // Transmit DMA instance number
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int8_t txCh; // Transmit channel number
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uint8_t txReq; // Transmit DMA request number
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void (*txCb)(uint32_t event); // Transmit callback
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DmaDescriptor_t *txDescriptor; // Tx descriptor
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DmaInstance_e rxInstance; // Receive DMA instance number
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int8_t rxCh; // Receive channel number
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uint8_t rxReq; // Receive DMA request number
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void (*rxCb)(uint32_t event); // Receive callback
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DmaDescriptor_t *rxDescriptor; // Rx descriptor
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} I2sDma_t;
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// I2S PINS
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typedef const struct
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{
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PIN *mclk; // main clk Pin identifier
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PIN *bclk; // pixel clk Pin identifier
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PIN *lrck; // cs Pin identifier
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PIN *din; // din Pin identifier
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PIN *dout; // dout Pin identifier
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} I2sPins_t;
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typedef struct
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{
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uint8_t busy; // Transmitter/Receiver busy flag
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uint8_t dataLost; // Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
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uint8_t modeFault; // Mode fault detected; optional (cleared on start of transfer operation)
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} I2sStatus_t;
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// I2S information (Run-time)
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typedef struct
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{
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i2sCbEvent_fn txCbEvent; // tx event callback
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i2sCbEvent_fn rxCbEvent; // rx event callback
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uint32_t mode; // I2S mode
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uint32_t busSpeed; // I2S bus speed
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uint16_t chainCnt;
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uint32_t totalNum; // Total length of audio source
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uint32_t trunkNum; // Trunk lengthe for every dma transfer
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uint32_t bps;
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uint32_t txDmaDescNum;
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uint32_t rxDmaDescNum;
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bool isEnableFracdiv;
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} I2sInfo_t;
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// I2S Resources definition
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typedef struct
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{
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I2S_TypeDef *reg; // I2S register pointer
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I2sPins_t pins; // I2S PINS configuration
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I2sDma_t *dma; // I2S DMA configuration pointer
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I2sInfo_t *info; // Run-Time Information
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} I2sResources_t;
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typedef enum
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{
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I2S_SLAVE_MODE = 0, ///< I2S is slave
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I2S_MASTER_MODE = 1, ///< I2S is master
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}I2sRole_e;
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typedef enum
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{
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MSB_MODE = 0, ///< Left aligned mode
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LSB_MODE = 1, ///< Right aligned mode
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I2S_MODE = 2, ///< I2S mode
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PCM_MODE = 3, ///< PCM mode
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}I2sMode_e;
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typedef enum
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{
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STOP_I2S = 0,
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ONLY_SEND = 1,
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ONLY_RECV = 2,
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SEND_RECV = 3,
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}I2sCtrlMode_e;
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// General power states
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typedef enum
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{
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I2S_POWER_OFF, // Power off: no operation possible
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I2S_POWER_FULL // Power on: full operation at maximum performance
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} I2sPowerState_e;
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// Access structure of the I2S Driver.
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typedef struct
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{
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int32_t (*init) (i2sCbEvent_fn txCbEvent, i2sCbEvent_fn rxCbEvent); // Initialize I2S Interface.
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int32_t (*deInit) (void); // De-initialize I2S Interface.
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int32_t (*powerCtrl) (I2sPowerState_e state); // Control I2S Interface Power.
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int32_t (*send) (bool needStop, bool needIrq, bool needChain, void *data, uint32_t chunkNum); // Start sending data from I2S Interface.
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int32_t (*recv) (bool needStop, bool needIrq, bool needChain, void *data, uint32_t chunkNum); // Start receiving data from I2S Interface.
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int32_t (*ctrl) (uint32_t control, uint32_t arg); // Control I2S Interface.
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uint32_t (*getTotalCnt)(void);
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uint32_t (*getTrunkCnt)(void);
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uint32_t (*getCtrlReg) (void);
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void (*stopDmaChannel) (void);
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} const I2sDrvInterface_t;
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typedef struct
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{
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uint32_t slaveModeEn : 1; // Slave Mode Enable
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uint32_t slotSize : 5; // Slot Size
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uint32_t wordSize : 5; // Word Size
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uint32_t alignMode : 1; // Align Mode
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uint32_t endianMode : 1; // Endian Mode
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uint32_t dataDly : 2; // Data Delay
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uint32_t txPad : 2; // Tx Padding
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uint32_t rxSignExt : 1; // Rx Sign extention
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uint32_t txPack : 2; // Tx Pack
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uint32_t rxPack : 2; // Rx Pack
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uint32_t txFifoEndianMode : 1; // Tx Fifo Endian Mode
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uint32_t rxFifoEndianMode : 1; // Rx Fifo Endian Mode
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}I2sDataFmt_t;
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// I2S Slot Control
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typedef struct
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{
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uint32_t slotEn : 8; // Slot Enable
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uint32_t slotNum : 3; // Slot number per frame synchronization
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}I2sSlotCtrl_t;
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// I2S Bclk Frame Synchronization Control
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typedef struct
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{
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uint32_t bclkPolarity : 1; // Bclk Polarity
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uint32_t fsPolarity : 1; // Frame Synchronization Polarity
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uint32_t fsWidth : 6; // Frame Synchronization width
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}I2sBclkFsCtrl_t;
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// I2S DMA Control
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typedef struct
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{
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uint32_t rxDmaReqEn : 1; // Rx Dma Req Enable
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uint32_t txDmaReqEn : 1; // Tx Dma Req Enable
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uint32_t rxDmaTimeOutEn : 1; // Rx Dma Timeout Enable
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uint32_t dmaWorkWaitCycle : 5; // Dma Work Wait Cycle
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uint32_t rxDmaBurstSizeSub1 : 4; // Rx Dma Burst Size subtract 1
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uint32_t txDmaBurstSizeSub1 : 4; // Tx Dma Burst Size subtract 1
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uint32_t rxDmaThreadHold : 4; // Rx Dma Threadhold
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uint32_t txDmaThreadHold : 4; // Tx Dma Threadhold
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uint32_t rxFifoFlush : 1; // Rx Fifo flush
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uint32_t txFifoFlush : 1; // Tx Fifo flush
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}I2sDmaCtrl_t;
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// I2S Interrupt Control
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typedef struct
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{
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uint32_t txUnderRunIntEn : 1; // Tx Underrun interrupt Enable
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uint32_t txDmaErrIntEn : 1; // Tx Dma Err Interrupt Enable
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uint32_t txDatIntEn : 1; // Tx Data Interrupt Enable
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uint32_t rxOverFlowIntEn : 1; // Rx Overflow Interrupt Enable
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uint32_t rxDmaErrIntEn : 1; // Rx Dma Err Interrupt Enable
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uint32_t rxDatIntEn : 1; // Rx Data Interrupt Enable
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uint32_t rxTimeOutIntEn : 1; // Rx Timeout Interrupt Enable
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uint32_t fsErrIntEn : 1; // Frame Start Interrupt Enable
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uint32_t frameStartIntEn : 1; // Frame End Interrupt Enable
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uint32_t frameEndIntEn : 1; // Frame End Interrupt Enable
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uint32_t cspiBusTimeOutIntEn : 1; // Not use
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uint32_t txIntThreshHold : 4; // Tx Interrupt Threadhold
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uint32_t rxIntThreshHold : 4; // Rx Interrupt Threadhold
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}I2sIntCtrl_t;
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// I2S Timeout Cycle
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typedef struct
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{
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uint32_t rxTimeOutCycle : 24; // Rx Timeout cycle
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}I2sTimeOutCycle_t;
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// I2S Status
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typedef struct
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{
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uint32_t txUnderRun : 1; // Tx Underrun
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uint32_t txDmaErr : 1; // Tx Dma Err
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uint32_t txDataRdy : 1; // Tx Data ready, readOnly
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uint32_t rxOverFlow : 1; // Rx OverFlow
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uint32_t rxDmaErr : 1; // Rx Dma Err
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uint32_t rxDataRdy : 1; // Rx Data ready, readOnly
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uint32_t rxFifoTimeOut : 1; // Rx Fifo timeout
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uint32_t fsErr : 4; // Frame synchronization Err
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uint32_t frameStart : 1; // Frame start
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uint32_t frameEnd : 1; // Frame end
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uint32_t txFifoLevel : 6; // Tx Fifo Level, readOnly
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uint32_t rxFifoLevel : 6; // Rx Fifo level, readOnly
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uint32_t cspiBusTimeOut : 1; // Not use
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}I2sStats_t;
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// I2S Control
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typedef struct
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{
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uint32_t i2sMode : 2; // I2S Mode
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}I2sCtrl_t;
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// I2S Auto Configure Control
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typedef struct
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{
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uint32_t autoCgEn : 1; // Auto Configure Enable
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}I2sAutoCgCtrl_t;
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/*----------------------------------------------------------------------------*
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* GLOBAL FUNCTIONS DECLEARATION *
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*----------------------------------------------------------------------------*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* BSP_I2S_H */
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