330 lines
15 KiB
C
330 lines
15 KiB
C
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#ifndef BSP_CSPI_H
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#define BSP_CSPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "stdio.h"
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#include "string.h"
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#include "ec7xx.h"
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#include "bsp.h"
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#define CSPI_TRANSFER_TRUNK_SIZE 7680 ///< Each DMA descriptor data size, fixed to 7680byte
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typedef void (*cspiCbEvent_fn) (uint32_t event); ///< cspi callback event.
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typedef void (*cspiSlp1Cb_fn)();
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extern cspiSlp1Cb_fn cspiSlp1CbFn;
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/****** CSPI Event *****/
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#define ARM_CSPI_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Data Transfer completed
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#define ARM_CSPI_EVENT_DATA_LOST (1UL << 1) ///< Data lost: Receive overflow / Transmit underflow
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#define ARM_CSPI_EVENT_MODE_FAULT (1UL << 2) ///< Master Mode Fault (SS deactivated when Master)
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/** \brief CSPI DMA */
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typedef struct
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{
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DmaInstance_e rxInstance; ///< Receive DMA instance number
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int8_t rxCh; ///< Receive channel number
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uint8_t rxReq; ///< Receive DMA request number
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void (*rxCb)(uint32_t event); ///< Receive callback
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DmaDescriptor_t *descriptor; ///< Rx descriptor
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} cspiDma_t;
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// CSPI PINS
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typedef const struct
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{
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PIN *mclk; ///< Main clk Pin identifier
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PIN *pclk; ///< Pixel clk Pin identifier
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PIN *cs; ///< Cs Pin identifier
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PIN *sdo0; ///< Din Pin identifier
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PIN *sdo1; ///< Dout Pin identifier
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} cspiPins_t;
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typedef struct
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{
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uint8_t busy; ///< Transmitter/Receiver busy flag
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} cspiRteStats_t;
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typedef enum
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{
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CAM_8W_Y = 10, // 8w only y use 10 dma descriptor chain
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CAM_8W_COLOR = 20, // 8w color use 20 dma descriptor chain
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CAM_30W_Y = 40, // 30w only y use 40 dma descriptor chain
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CAM_30W_COLOR = 80, // 30w use 80 dma descriptor chain
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}camResolution_e;
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typedef enum
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{
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CAM_6_5_M = 0, ///< camera 6.5M HZ
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CAM_13_M = 1, ///< camera 13M HZ
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CAM_25_5_M = 2, ///< camera 25.5M HZ
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CAM_24_M = 3, ///< camera 24M HZ
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}camFrequence_e;
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// CSPI information (Run-time)
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typedef struct
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{
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cspiCbEvent_fn cbEvent; ///< Event callback
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cspiRteStats_t status; ///< CSPI status flags
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uint8_t flags; ///< CSPI driver flags
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uint32_t busSpeed; ///< CSPI bus speed
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uint8_t dataWidth; ///< CSPI data bits select in unit of byte
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uint32_t targetAddr; ///< CSPI target address
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camResolution_e resolution; ///< Camera resolution
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} cspiInfo_t;
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// SPI Resources definition
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typedef struct
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{
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CSPI_TypeDef *reg; ///< SPI register pointer
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cspiPins_t pins; ///< SPI PINS configuration
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cspiDma_t *dma; ///< SPI DMA configuration pointer
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cspiInfo_t *info; ///< Run-Time Information
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} cspiRes_t;
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/**
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\brief General power states
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*/
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typedef enum
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{
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CSPI_POWER_OFF, ///< Power off: no operation possible
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CSPI_POWER_FULL ///< Power on: full operation at maximum performance
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} cspiPowerState_e;
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typedef struct
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{
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uint32_t slaveModeEn : 1; ///< Slave Mode Enable
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uint32_t slotSize : 5; ///< Slot Size
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uint32_t wordSize : 5; ///< Word Size
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uint32_t alignMode : 1; ///< Align Mode
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uint32_t endianMode : 1; ///< Endian Mode
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uint32_t dataDly : 2; ///< Data Delay
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uint32_t txPad : 2; ///< Tx padding
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uint32_t rxSignExt : 1; ///< Rx Sign Entension
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uint32_t txPack : 2; ///< Tx Pack
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uint32_t rxPack : 2; ///< Rx Pack
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uint32_t txFifoEndianMode : 1; ///< Tx Fifo Endian Mode
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uint32_t rxFifoEndianMode : 1; ///< Rx Fifo Endian Mode
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uint32_t eorMode : 1; ///< eor
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}cspiDataFmt_t;
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typedef struct
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{
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uint32_t slotEn : 3; ///< Slot Enable
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uint32_t slotNum : 8; ///< Slot Num
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}cspiSlotCtrl_t;
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typedef struct
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{
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uint32_t bclkPolarity : 1; ///< Bclk Polarity
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uint32_t fsPolarity : 1; ///< Frame Synchronization Polarity
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uint32_t fsWidth : 6; ///< Frame Synchronization Width
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}cspiBclkFsCtrl_t;
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typedef struct
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{
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uint32_t rxDmaReqEn : 1; ///< Rx Dma Req Enable
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uint32_t txDmaReqEn : 1; ///< Tx Dma Req Enable
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uint32_t rxDmaTimeOutEn : 1; ///< Rx Dma Timeout Enable
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uint32_t dmaWorkWaitCycle : 5; ///< Dma Work Wait Cycle
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uint32_t rxDmaBurstSizeSub1 : 4; ///< Rx Dma Burst Size subtract 1
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uint32_t txDmaBurstSizeSub1 : 4; ///< Tx Dma Burst Size subtract 1
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uint32_t rxDmaThreadHold : 4; ///< Rx Dma Threadhold
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uint32_t txDmaThreadHold : 4; ///< Tx Dma Threadhold
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uint32_t rxFifoFlush : 1; ///< Rx Fifo flush
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uint32_t txFifoFlush : 1; ///< Tx Fifo flush
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}cspiDmaCtrl_t;
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typedef struct
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{
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uint32_t txUnderRunIntEn : 1; ///< Tx Underrun interrupt Enable
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uint32_t txDmaErrIntEn : 1; ///< Tx Dma Err Interrupt Enable
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uint32_t txDatIntEn : 1; ///< Tx Data Interrupt Enable
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uint32_t rxOverFlowIntEn : 1; ///< Rx Overflow Interrupt Enable
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uint32_t rxDmaErrIntEn : 1; ///< Rx Dma Err Interrupt Enable
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uint32_t rxDatIntEn : 1; ///< Rx Data Interrupt Enable
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uint32_t rxTimeOutIntEn : 1; ///< Rx Timeout Interrupt Enable
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uint32_t fsErrIntEn : 1; ///< Frame Start Interrupt Enable
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uint32_t frameStartIntEn : 1; ///< Frame End Interrupt Enable
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uint32_t frameEndIntEn : 1; ///< Frame End Interrupt Enable
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uint32_t cspiBusTimeOutIntEn : 1; ///< Not use
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uint32_t rsvd1 : 4; ///< For lspi
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uint32_t otsuEndEn : 1; ///< OTSU end
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uint32_t rsvd2 : 1; ///< For lspi
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uint32_t txIntThreshHold : 4; ///< Tx Interrupt Threadhold
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uint32_t rxIntThreshHold : 4; ///< Rx Interrupt Threadhold
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}cspiIntCtrl_t;
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typedef struct
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{
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uint32_t rxTimeOutCycle : 24; ///< Rx Timeout Cycle
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uint32_t dummyCycle : 4;
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}cspiTimeOutCycle_t;
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typedef struct
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{
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uint32_t txUnderRun : 1; ///< Tx Underrun
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uint32_t txDmaErr : 1; ///< Tx Dma Err
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uint32_t txDataRdy : 1; ///< Tx Data ready, readOnly
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uint32_t rxOverFlow : 1; ///< Rx OverFlow
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uint32_t rxDmaErr : 1; ///< Rx Dma Err
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uint32_t rxDataRdy : 1; ///< Rx Data ready, readOnly
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uint32_t rxFifoTimeOut : 1; ///< Rx Fifo timeout
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uint32_t fsErr : 4; ///< Frame synchronization Err
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uint32_t frameStart : 1; ///< Frame start
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uint32_t frameEnd : 1; ///< Frame end
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uint32_t txFifoLevel : 6; ///< Tx Fifo Level, readOnly
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uint32_t rxFifoLevel : 6; ///< Rx Fifo level, readOnly
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uint32_t cspiBusTimeOut : 1; ///< Cspi Bus timeout
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uint32_t rsvd1 : 3; ///< For lspi
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uint32_t otsuEnd : 1; ///< cspi OTSU end
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uint32_t rsvd2 : 2; ///< For lspi
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}cspiStats_t;
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typedef struct
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{
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uint32_t enable : 1; ///< Enable
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uint32_t csEn : 1; ///< CS signal check
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uint32_t rxWid : 1; ///< Rx Width
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uint32_t rxdSeq : 1; ///< Rx Sequence
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uint32_t cpol : 1; ///< SPI polarity
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uint32_t cpha : 1; ///< SPI phase
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uint32_t frameProcEn : 1; ///< Frame Process Enable
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uint32_t fillYonly : 1; ///< Fill Y Only
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uint32_t hwInitEn : 1; ///< HW Init Enable
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uint32_t lsCheckEn : 1; ///< Line Start Check Enable
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uint32_t dpCheckEn : 1; ///< Data Pcket Check Enable
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uint32_t frameProcInitEn : 1; ///< Frame Process Init Enable
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uint32_t rowScaleRatio : 4; ///< Row Scale Ratio
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uint32_t colScaleRatio : 4; ///< Column Scale Ratio
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uint32_t scaleBytes : 2; ///< Scale Bytes
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uint32_t otsuDummyLineCnt : 6; ///< OTSU dummy line count
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uint32_t otsuEn : 1; ///< OTSU enable
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uint32_t otsuEnClrEn : 1; ///< OTSU enable bit cleared by HW or SW
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uint32_t otsuCalYAdjEn : 1; ///< Calculate y stretch for OTSU
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uint32_t ddrMode : 1; ///< DDR mode
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}cspiCtrl_t;
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typedef struct
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{
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uint32_t autoCgEn : 1; ///< Auto Configure Enable
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}cspiAutoCgCtrl_t;
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typedef struct
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{
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uint32_t cspiBusTimeOutCycle : 24; ///< Cspi Bus Timeout Cycle
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uint32_t dataId : 8; ///< Data Indication, readOnly
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}cspiFrameInfo0_t;
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typedef struct
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{
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uint32_t cspiInit : 1; ///< Cspi Init
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}cspiInit_t;
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typedef struct
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{
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uint32_t binaryThresholdInUse : 8; ///< Binary threshold in use
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uint32_t otsuThreshold : 8; ///< Threshold calculated by OTSU
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uint32_t binaryThreshold : 8; ///< Threshold calculated by SW
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uint32_t binaryThresholdSel : 1; ///< Threshold by HW or SW
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uint32_t outSwCtrl : 2; ///< Data give for Rxfifo and whether need to binary
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uint32_t outSwClrEn : 1; ///< Whether HW can clear the cspi_out_sw_ctrl bit
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uint32_t dummyAllowed : 1;
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uint32_t wordIdSeq : 1;
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}cspiBinaryCtrl_t;
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typedef struct
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{
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uint32_t outEnLspi : 1; ///< 1: out for lspi; 0: not out for lspi
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uint32_t outEnLspiClrEn : 1; ///< Clear cspiOutEnLspi by HW(1) or SW(0)
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uint32_t fillYOnlyLspi : 1; ///< 0: not cut UV; 1: cut UV, only retain Y
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uint32_t rsvd : 5;
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uint32_t rowScaleRatioLspi : 4; ///< Every "rowScaleRatioLspi" lines receive next line. 0: not scale
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uint32_t colScaleRatioLspi : 4; ///< Every "colScaleRatioLspi" pixels receive next pixel in a line. 0: not scale
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}cspiFrameProcLspi_t;
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typedef struct
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{
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uint32_t i2sBusEn : 1; ///< I2S bus enable
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uint32_t cspiBusEn : 1; ///< Cspi bus enable
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uint32_t lspiBusEn : 1; ///< Lspi bus enable
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}cspiBusSel_t;
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typedef struct
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{
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uint32_t clkDelay : 3;
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uint32_t : 1;
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uint32_t csnDelay : 3;
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uint32_t : 1;
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uint32_t rx0Delay : 3;
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uint32_t : 1;
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uint32_t rx1Delay : 3;
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uint32_t : 1;
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uint32_t clkDefaultVal : 1;
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uint32_t csnDefaultVal : 1;
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uint32_t rx0DefaultVal : 1;
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uint32_t rx1DefaultVal : 1;
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}cspiDelayCtrl_t;
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typedef struct
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{
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uint32_t histogramBufSwMode : 1; ///< HW or SW access histogram buffer
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}histogramBufSwMode_t;
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/**
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\brief Cspi control bits.
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*/
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#define CSPI_CTRL_TRANSABORT (1UL << 0) ///< CSPI trans abort
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#define CSPI_CTRL_BUS_SPEED (1UL << 1) ///< CSPI trans abort
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#define CSPI_CTRL_DATA_BITS (1UL << 2) ///< CSPI trans abort
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#define CSPI_CTRL_DATA_FORMAT (1UL << 3) ///< CSPI data format
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#define CSPI_CTRL_SLOT_CTRL (1UL << 4) ///< CSPI slot ctrl
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#define CSPI_CTRL_BCLK_FS_CTRL (1UL << 5) ///< CSPI bclk fs ctrl
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#define CSPI_CTRL_DMA_CTRL (1UL << 6) ///< CSPI dma ctrl
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#define CSPI_CTRL_INT_CTRL (1UL << 7) ///< CSPI int ctrl
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#define CSPI_CTRL_TIMEOUT_CYCLE (1UL << 8) ///< CSPI timeout cycle
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#define CSPI_CTRL_STATUS (1UL << 9) ///< CSPI status
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#define CSPI_CTRL_CSPICTL (1UL << 10) ///< CSPI control
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#define CSPI_CTRL_AUTO_CG_CTRL (1UL << 11) ///< CSPI auto cg ctrl
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#define CSPI_CTRL_FRAME_INFO0 (1UL << 12) ///< CSPI frame info0
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#define CSPI_CTRL_INIT (1UL << 13) ///< CSPI init
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#define CSPI_CTRL_RXTOR (1UL << 14) ///< CSPI rx timeout cycle
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#define CSPI_CTRL_MEM_ADDR (1UL << 15) ///< CSPI memory addr set
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#define CSPI_CTRL_FLUSH_RX_FIFO (1UL << 16) ///< Flush rx fifo
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#define CSPI_CTRL_START_STOP (1UL << 17) ///< Start or stop cspi
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#define CSPI_CTRL_RESOLUTION_SET (1UL << 18) ///< Camera resolution set
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#define CSPI_BINARY_CTRL (1UL << 19) ///< CSPI binary control
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#define CSPI_FRAME_PROC_LSPI (1UL << 20) ///< CSPI out for LSPI
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#define CSPI_DELAY_CTRL (1UL << 21) ///< CSPI delay ctrl
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/**
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\brief Access structure of the CSPI Driver.
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*/
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typedef struct
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{
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int32_t (*init) (cspiCbEvent_fn cb_event); ///< Initialize CSPI Interface.
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int32_t (*deInit) (void); ///< De-initialize CSPI Interface.
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int32_t (*powerCtrl) (cspiPowerState_e state); ///< Control CSPI Interface Power.
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int32_t (*recv) (void); ///< Open dma to receive data.
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int32_t (*ctrl) (uint32_t control, uint32_t arg); ///< Control CSPI Interface.
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} const cspiDrvInterface_t;
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#ifdef __cplusplus
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}
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#endif
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#endif
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