165 lines
5.5 KiB
C
165 lines
5.5 KiB
C
/****************************************************************************
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*
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* Copy right: 2018-, Copyrigths of EigenComm Ltd.
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* File name: ic.h
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* Description: EC718 interrupt controller header file
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* History: Rev1.0 2018-11-15
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*
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****************************************************************************/
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#ifndef _IC_EC7XX_H
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#define _IC_EC7XX_H
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#include "ec7xx.h"
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#include "Driver_Common.h"
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/**
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\addtogroup xic_interface_gr
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\{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#ifdef TYPE_EC718M
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#define NUM_APXIC_MODULE (5U) /**< number of XIC module */
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#else
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#define NUM_APXIC_MODULE (4U) /**< number of XIC module */
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#endif
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#define NUM_APXIC0_INT (32U) /**< number of interrupts in XIC0 */
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#define NUM_APXIC1_INT (32U) /**< number of interrupts in XIC1 */
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#define NUM_APXIC2_INT (32U) /**< number of interrupts in XIC2 */
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#define NUM_APXIC3_INT (32U) /**< number of interrupts in XIC3 */
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#define NUM_APXIC4_INT (32U) /**< number of interrupts in XIC4 */
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#define MAX_NUM_XIC_INT (32U) /**< maximum number of interrupts in XIC */
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/** ISR function type define */
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typedef void ( *ISRFunc_T )(void);
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/*******************************************************************************
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* API
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******************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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\fn void IC_PowupInit(void)
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\brief Initialize the interrupt controller, including HW configuration and ISR initialization,
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called when POR or wakeup from Hibernate, in which the SRAM contents have been lost.
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*/
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void IC_PowupInit(void);
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/**
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\fn void IC_Powoff(void)
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\brief DeInitialize the interrupt controller, including HW configuration and ISR initialization.
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*/
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void IC_Powoff(void);
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/**
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\fn void XIC_SetVector(IRQn_Type IRQn, ISRFunc_T vector)
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\brief Sets an XIC interrupt vector in SRAM based interrupt vector table.
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Use this function to bind the XIC interrupt and application ISR.
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\param[in] IRQn Interrupt number
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\param[in] vector Address of interrupt handler function
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\note The interrupt number must be positive
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*/
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void XIC_SetVector(IRQn_Type IRQn, ISRFunc_T vector);
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/**
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\fn void XIC_EnableIRQ(IRQn_Type IRQn)
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\brief Enables a device specific interrupt in the XIC interrupt controller.
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\param[in] IRQn Interrupt number
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\note The interrupt number must be positive
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*/
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void XIC_EnableIRQ(IRQn_Type IRQn);
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/**
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\fn void XIC_DisableIRQ(IRQn_Type IRQn)
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\brief Disables a device specific interrupt in the XIC interrupt controller.
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\param[in] IRQn Interrupt number
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\note The interrupt number must be positive
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*/
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void XIC_DisableIRQ(IRQn_Type IRQn);
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/**
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\fn void XIC_BackupIRQSetting(uint32_t *mask_array, uint32_t *clrovf_array)
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\brief backup the interrupt mask and ovf setting before sleep
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\param[out] mask_array mask0, mask1, clrovf0 to store the irq mask and ovf setting
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\param[out] clrovf_array
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\note
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*/
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void XIC_BackupIRQSetting(uint32_t *mask_array, uint32_t *clrovf_array);
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/**
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\fn void XIC_RestoreIRQSetting(uint32_t *mask_array, uint32_t *clrovf_array)
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\brief restore the interrupt mask and ovf setting after sleep
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\param[in] mask_array mask0, mask1, clrovf0 is the stored value before sleep
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\param[out] clrovf_array
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\note
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*/
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void XIC_RestoreIRQSetting(uint32_t *mask_array, uint32_t *clrovf_array);
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/**
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\fn void XIC_SetPendingIRQ(IRQn_Type IRQn)
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\brief Sets the pending bit of a device specific interrupt in the XIC pending register,
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mainly used for SW generating interrupt.
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\param[in] IRQn Interrupt number
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\note The interrupt number must be positive
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*/
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void XIC_SetPendingIRQ(IRQn_Type IRQn);
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/**
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\fn void XIC_ClearPendingIRQ(IRQn_Type IRQn)
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\brief Clears the pending bit of a device specific interrupt in the XIC pending register.
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\param[in] IRQn Interrupt number
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\note The interrupt number must be positive
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*/
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void XIC_ClearPendingIRQ(IRQn_Type IRQn);
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/**
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\fn uint32_t XIC_LatchIRQ(XIC_TypeDef* xic)
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\brief Latch the pending interrupt status to the latch register and read out.
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\param[in] xic Pointer to XIC instance
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\return Interrupt status
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*/
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uint32_t XIC_LatchIRQ(XIC_TypeDef* xic);
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/**
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\fn void XIC_SuppressOvfIRQ(IRQn_Type IRQn)
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\brief Suppress overflow IRQ
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\param[in] IRQn Interrupt number
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\note The interrupt number must be positive
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*/
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void XIC_SuppressOvfIRQ(IRQn_Type IRQn);
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/**
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\fn void XIC_ClearAllPendingIRQ(XIC_TypeDef* xic)
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\brief Clears all pending bits of a XIC interrupt controller.
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\param[in] xic Pointer to XIC instance
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*/
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void XIC_ClearAllPendingIRQ(XIC_TypeDef* xic);
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/**
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\fn void XIC_DisableAllIRQExceptUart(void)
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\brief disable all interrupt except PXIC0_UART0_IRQn/PXIC0_UART1_IRQn/PXIC0_UART2_IRQn/PXIC1_DMA_MP_IRQn
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*/
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void XIC_DisableAllIRQExceptUart(void);
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/**
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\fn void XIC_RestoreAllIRQ(void)
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\brief restore interrupt settings, call after XIC_DisableAllIRQExceptUart
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*/
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void XIC_RestoreAllIRQ(void);
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/** \} */
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#ifdef __cplusplus
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}
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#endif
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#endif
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